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ISL58214
TABLE 14. HFM FREQUENCY COUNT REGISTER (WRITE MODE) (REG 1-0E)
BIT
B7 - B2
B1
B0
BIT
B7 - B0
BIT
B7 - B0
BIT
B7
B6 - B5
B4 - B0
NAME
Reserved
Enable Serial HFM Count
SCLK Mode
NAME
Device ID
NAME
Revision ID
NAME
LD Sample Ena
Reserved
QD4 - QD0
BIT DEFINITION
If B1 = 1, the HFM counter will count when SCLK is high.
If B1 = 0, the HFM counter will not count.
IF B1 above = 1, and B0 = 0, SCLK is the interval for the HFM frequency count.
If B1 above = 1, and B0 = 1, SCLK/2 is the interval for the HFM frequency count (two SCLK periods).
TABLE 15. DEVICE ID (REG 1-15)
BIT DEFINITION
Device ID = 0x77 A different number is available for each chip family.
TABLE 16. REVISION ID (REG 1-16)
BIT DEFINITION
This Rev ID is 0xC8 A number to identify the member of the device family.
TABLE 17. WRITE Q DAMPING AND LD SAMPLE (REG 1-17)
BIT DEFINITION
B7 = 1 means that laser voltage sampling is enabled.
B7 = 0 means that laser voltage sampling is disabled.
Do not use
Write “Q” Damping for Iout1 is related to (16 QD4 + 8 QD3 + 4 QD2 + 2 QD1 + QD0). A larger number
provides more damping.
TABLE 18. SPREAD SPECTRUM CONTROL (REG 1-18)
BIT
B7
B6 - B4
B3 - B0
NAME
SS Frequency and Disable
SS Width
Reserved
BIT DEFINITION
If bits B7, B6, B5, and B4 are all 0, the SS is disabled. If SS width is non zero, this bit selects about
34kHz when 1, and about 53kHz when 0.
Width ? k (24B6 + 2 B5 + B4)
Do not use
TABLE 19. THRESHOLD AND SCALE DAC GAIN SELECT (REG 1-21)
BIT
B7 - B4
B3 - B0
NAME
I THRESHOLD GAIN
I SNK_MAX
15
BIT DEFINITION
The Gain of the threshold amplifier is = K(8B7 + 4B6 + 2B5 + B4). The power-up register value is 1000.
A setting of 0000 defaults to a setting of 0001 to prevent zero gain.
If I SNK output is selected, these 4 bits multiply by the existing SCALE output to determine the I SNK fast
current. The power-up register value is 1000. A setting of 0000 defaults to a setting of 0001 to prevent
zero gain.
If I SRC is selected, these bits should be 0000.
FN6944.1
July 29, 2013
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